Active-HDL 5.2 Release Gives Unprecedented Simulation Boost to FPGA Designs
Henderson Nevada, August 26, 2002 -- Aldec, Inc., a pioneer in mixed language simulation and advanced design tools for FPGA and ASIC devices, today announced commercial release of its Active-HDL 5.2 FGPA design and verification software. Active-HDL 5.2 is now available for shipment and contains its fully integrated simulation kernel, which can concurrently simulate VHDL, Verilog and EDIF. 90% of participants in the Active-HDL 5.2 beta release program held earlier this summer reported dramatic simulation acceleration in their entire design cycle.
The advancements in Active-HDL 5.2 provide industry-leading performance not only in verification times, but its new features simplify the design creation process and ensure that the most efficient end-devices result from the tool suite. Verilog 2001 constructs support has been added to ensure that designers are using the most widely-recognized and accepted design standards in the EDA industry.
Simulation times in Active-HDL have been further accelerated over previous versions, particularly in regards to Verilog designs. Active-HDL 5.2 is especially useful when designing very dense FPGAs or FPGAs that have been partitioned by multiple design teams. Active-HDL 5.2's vendor independence makes it an ideal cross-over tool for designers because its advanced interface can support any combination of synthesis and implementation tools, giving designers the flexibility to target multiple silicon vendors depending on their current design needs.
Design and verification advancements in Active-HDL 5.2 are among the most advanced in the industry; all of the new features present in Active-HDL 5.2 were added in respect to its simulation kernel so that running even the most advanced UI features does not adversely affect overall run times.
"It's quite an accomplishment that our development team was able to introduce so many advanced features into the GUI without decreasing overall run-times of the tool. In fact, Active-HDL 5.2's simulation kernel is the fastest on the market to date and Verilog users particularly will notice a simulation speed up in excess of 2x," stated Megan Moran, Product Marketing Manager for Active-HDL.
Multi-Design Workspace
The Multi-Design Workspace feature allows designers to open several discrete designs within the same Active-HDL environment. Designers can simultaneously open multiple designs and integrate them into one super-project. In this environment, users can manage among all of the loaded designs, switch among them, edit their resources and configure them independently. Designers working as a team on the same project can share their modules with their peers and managers. All modules can be designed separately and then integrated together as one top-level design. There is no risk of mistakenly modifying the incorrect design because only the design that is set as active is capable of being changed. Multi-Design Workspace also aids in library management, as all libraries are now set as global until an active design invokes the particular library that it will be needing.
Export2HTML
The Export2HTML feature allows designers to export their design files into an external .html file. The file can then be viewed on any web browser and does not necessitate a connection to the tool. Users can fully navigate the design through the html files, as graphical elements can still be pushed into to show the corresponding code and hierarchies may be changed in FSMs. Export2HTML maintains an identical look and structure to the html pages as if they were being viewed directly in the Active-HDL environment and is the ideal tool for extensive documentation.
Random Signal Generator
The Random Signal Generator simplifies the creation of testbenches. The Random Signal Generator allows users to simulate unpredictable events in designs more accurately by using pseudo-random generation algorithms. The designer can set up a signal generator for various data bits and the system will generate data automatically.
Memory Viewer
The Memory Viewer is a new debugging tool that displays the contents of memories in a tabular format. The memories' types, depths and address ranges can be observed during simulation. The Memory Viewer also allows users to edit the value of a memory and save the modified contents in an external text file. Designers may also drag and drop memory objects in order to isolate the specific memories that they are interested in. The Memory Viewer is fully configurable and provides a concise medium for designers to view contents rather than having to decipher memory results from waveform results.
Preferences Manager
The Preference Manager aids users in migrating to different versions of Active-HDL; user settings can now be exported into an external file and applied to the new software with the help of a GUI Wizard. Users switching versions of the tool no longer have to manually set their preferences and can transfer setting information from one version to the next.
The release of Active-HDL 5.2 incorporates the fastest simulation support with the strongest feature set on the market. Active-HDL 5.2's expanded support of third-party tools makes it a universal tool for all FPGA designs.
Availability
Active-HDL 5.2 is available now and can be ascribed to either a floating or node-lock license for no additional revenue. Active-HDL 5.2 includes Multi-Design Workspace, HDL Editor, State Machine Editor, and Block Diagram & Schematic Editors, Automatic Testbench Generation, Waveform Viewer/Editor, and a choice of VHDL, Verilog or mixed VHDL/Verilog/EDIF simulation. All sales include one year of product maintenance. To receive your FREE evaluation copy, contact Aldec at www.aldec.com.
About Aldec
Aldec, Inc., an 18-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers' needs. It is recognized that to be productive in today's market and to best serve customers in the future, new technologies and innovations that go beyond traditional methods of conducting business in the EDA industry must be pursued. Aldec is committed to customer service and is actively developing a company that will evolve along with its customers' designs. Additional information about Aldec is available at http://www.aldec.com.
Active-HDL is a trademark of Aldec, Inc.
